The present disclosure relates to integrated circuit device reliability in radio frequency (RF) applications and, more specifically, to a structure, system and method for stressing and characterizing integrated circuit devices to be used in RF applications. Typically, reliability data for integrated circuit devices (e.g., field effect transistors (FETs), resistors, capacitors, etc.) is captured under direct current (DC) conditions and used to make accurate useful life predictions for both DC applications and digital applications. However, such DC reliability data (i.e., reliability data captured under DC conditions) is not sufficient for making useful life predictions when the integrated circuit devices are to be used in RF applications. For example, in an RF application, the RF swing voltage may exceed the maximum allowable DC bias voltage for a given device and can change the degradation of the given device due to various different failure mechanisms (e.g., hot carrier degradation, time-dependent dielectric breakdown, etc.) so as to change the useful life of the given device and, thereby the useful life of any integrated circuit structure that incorporates it. In order to understand the failure mechanisms and, thereby predict the useful life of an integrated circuit device in an RF application, a test structure must be deployed and stressed under RF power. Several prior art techniques have been proposed for stressing and characterizing an integrated circuit device under RF power, but these techniques do not separate particular failure mechanisms, do not account for impedance mismatch, and/or, if they do account for impedance mismatch, require complicated impedance tuning processes in order to avoid impedance mismatch. Thus, there is a need in the art for improved structures, systems and methods for stressing and characterizing integrated circuit devices to be used in RF applications.